SignalCNN MAC ASIC Hardening
A Formal Proof Must Also Catch the Deliberately Broken Chip
A chip equivalence proof now has to fail on a planted bug before its passing result counts.
Intelligence layer v0.2.0
The intelligence layer for hardware development.
Hardware is catching up to software. hw.dev tracks where that is happening, where it is still broken, and what builders should do about it.
WorldviewSoftware-first. Operator-led. Everything-as-code.
CadenceSignal daily. Analysis weekly. Stack Maps as the ground moves.
LensProduct realization, test, AI, supply, PLM/CAD/ERP displacement.
Thesis
Hardware isn't slow because of physics. It's slow because of coordination, validation, and tooling.
Those constraints are starting to break.
The bottleneck is shifting to decision-making. The teams that win will be the ones that compress the loop:
ideavalidationdecision
Latest Signal
Short posts on meaningful developments. What happened, why it matters, what it enables, operator read.
SignalConsortium
An i.MX 95 Hardware Test Finds Stale Memory and a Masked Interrupt
A two-core board test exposed three failures that simulation and a clean boot would have hidden.
SignalHardware Designer Template
KiCad Rules Get Tested on a Board Before They Reach the Review
A KiCad rule now has to face the real board before an engineer trusts the prose that describes it.
SignalSilinx ISE
An Open Spartan-3E Router Recovers 104 Megahertz After the First Router Gives Up
A measured fallback router makes an old programmable chip faster, and the benchmark now guards that gain.
Featured Analysis
Long-form essays on the shifts reshaping hardware development. What is changing, why now, who benefits, what builders should do.
Analysis6 min read
Hardware Tests Are Starting to Travel With the Product
One test definition can now move from software model to prototype board, production line, and field.
Analysis6 min read
PCB Review Is Becoming a Build Step
Open tools are turning electrical, manufacturing, and mechanical review comments into checks that run on every board change.
Stack Maps
Opinionated, living reference maps of the modern hardware development stack. Layers. Incumbents. Insurgents. Named gaps.
Stack Map
Modern Hardware Development Stack
First cut at the layered map of modern hardware development (from design through manufacture) with named incumbents, insurgents, and gaps. Updated as the ground moves.
Planned
Modern Hardware Development Stack
The end-to-end stack a modern hardware team actually runs on: design, simulation, test, CI, manufacturing. Layered, opinionated, with named gaps.
Planned
AI in Hardware Development
Where AI is actually compressing hardware cycle time today, layer by layer: RTL, place-and-route, DV, PCB, DFM, test authoring, supply.
Planned
Shift-Left Testing Stack
The stack that lets every test run in CI, not a lab bench: unit, integration, HIL, on-target, and compliance. Where the gaps are.
Planned
Validation-as-Code Stack
What validation looks like when specs, tests, coverage, and sign-off artifacts all live in Git. The tools, the formats, the missing layer.
Planned
Product Realization Stack
The workflow from idea to shipped unit (requirements, CAD, BOM, MFG, field) and which layers have been code-ified vs which are still PDFs in SharePoint.
About hw.dev
hw.dev is operator-led. Software-first view of hardware. Everything-as-code. Shift-left testing. Product realization.
Not a news site. Not an aggregator. An intelligence layer: Signal to read the week, Analysis to read the shift, Stack Maps to read the space.
Future tools may include BOM Intelligence, Test Intelligence, Validation Intelligence, Supply Chain Intelligence, and Product Realization Intelligence. Intelligence is the identity; the tools are the follow-through.