SignalautoMBIST
autoMBIST Turns Memory Repair Into Reproducible Yield Curves
Memory redundancy can now be evaluated against modeled defects before a team commits spare rows and columns to silicon.
Intelligence layer v0.2.0
The intelligence layer for hardware development.
Hardware is catching up to software. hw.dev tracks where that is happening, where it is still broken, and what builders should do about it.
WorldviewSoftware-first. Operator-led. Everything-as-code.
CadenceSignal daily. Analysis weekly. Stack Maps as the ground moves.
LensProduct realization, test, AI, supply, PLM/CAD/ERP displacement.
Thesis
Hardware isn't slow because of physics. It's slow because of coordination, validation, and tooling.
Those constraints are starting to break.
The bottleneck is shifting to decision-making. The teams that win will be the ones that compress the loop:
ideavalidationdecision
Latest Signal
Short posts on meaningful developments. What happened, why it matters, what it enables, operator read.
SignalQualcomm
Qualcomm Lets Embedded Linker Plugins Build Outside Its Source Tree
Embedded Linker extensions can now compile against an installed public interface instead of a private copy of the whole toolchain.
SignalReticle
Reticle Cuts a Zynq Programmable-Logic Route From 14 Minutes to 2.5
One corrected physical model cut a real routing search by 46 times and exposed why open chip tools need measurable device models.
SignalSerialtap
Serialtap Keeps USB Board Identity Stable Across Windows Replugs
A Windows identity fix keeps logs and device names attached to the same development board after ports and drivers change.
Featured Analysis
Long-form essays on the shifts reshaping hardware development. What is changing, why now, who benefits, what builders should do.
Analysis7 min read
In Hardware AI, the Checker Matters More Than the Agent
Siemens, Synopsys, RISC-V, and Pasqal all let an AI agent do the work while a separate, trusted tool decides whether it counts. That tool is where the lasting value is.
Analysis6 min read
The Verified Handoff Is Becoming the Hardware Product
Arm, Rapidus, SEMIFIVE, and AMD are converging on the same model: sell an integration contract, not a component.
Stack Maps
Opinionated, living reference maps of the modern hardware development stack. Layers. Incumbents. Insurgents. Named gaps.
Stack Map
Modern Hardware Development Stack
First cut at the layered map of modern hardware development (from design through manufacture) with named incumbents, insurgents, and gaps. Updated as the ground moves.
Planned
Modern Hardware Development Stack
The end-to-end stack a modern hardware team actually runs on: design, simulation, test, CI, manufacturing. Layered, opinionated, with named gaps.
Planned
AI in Hardware Development
Where AI is actually compressing hardware cycle time today, layer by layer: RTL, place-and-route, DV, PCB, DFM, test authoring, supply.
Planned
Shift-Left Testing Stack
The stack that lets every test run in CI, not a lab bench: unit, integration, HIL, on-target, and compliance. Where the gaps are.
Planned
Validation-as-Code Stack
What validation looks like when specs, tests, coverage, and sign-off artifacts all live in Git. The tools, the formats, the missing layer.
Planned
Product Realization Stack
The workflow from idea to shipped unit (requirements, CAD, BOM, MFG, field) and which layers have been code-ified vs which are still PDFs in SharePoint.
About hw.dev
hw.dev is operator-led. Software-first view of hardware. Everything-as-code. Shift-left testing. Product realization.
Not a news site. Not an aggregator. An intelligence layer: Signal to read the week, Analysis to read the shift, Stack Maps to read the space.
Future tools may include BOM Intelligence, Test Intelligence, Validation Intelligence, Supply Chain Intelligence, and Product Realization Intelligence. Intelligence is the identity; the tools are the follow-through.