Hardware is catching up to software. hw.dev tracks where that is happening, where it is still broken, and what builders should do about it.
Hardware isn't slow because of physics. It's slow because of coordination, validation, and tooling.
Those constraints are starting to break.
The bottleneck is shifting to decision-making. The teams that win will be the ones that compress the loop:
Short posts on meaningful developments. What happened, why it matters, what it enables, operator read.
ETH Zurich tapes out Chimera, a 22nm FDX AI-MCU with nine RISC-V cores and a tightly-coupled transformer accelerator, hitting 3.1 TOPS/W and 100x better area efficiency than standalone SoCs -- closing the argument that flexible and efficient are mutually exclusive.
Researchers show that element-level sparsity in diffusion models overstates hardware-exploitable sparsity by up to 78 percentage points on systolic-array accelerators, and that memory stalls account for 84-89% of total cycles -- meaning most accelerator sparsity marketing is measuring the wrong thing.
Nordic hooks MCP servers into nRF Connect SDK and nRF Cloud so AI assistants operate on validated primary-source context instead of stale training data, removing the documentation-as-a-PDF bottleneck in embedded firmware development.
Itera just came out of stealth with reconfigurable circuit boards whose liquid-metal tracks and vias rewire on demand in under 60 seconds, attacking the single biggest delay in hardware prototyping and removing the constraint that every routing change costs a board spin.
Long-form essays on the shifts reshaping hardware development. What is changing, why now, who benefits, what builders should do.
The verification coordination wall is real, it is getting worse, and the sign-off gate is where the value gets captured.
The RVA23 profile mandate settled the portability argument that held RISC-V at bay from production embedded Linux
Opinionated, living reference maps of the modern hardware development stack. Layers. Incumbents. Insurgents. Named gaps.
First cut at the layered map of modern hardware development (from design through manufacture) with named incumbents, insurgents, and gaps. Updated as the ground moves.
The end-to-end stack a modern hardware team actually runs on: design, simulation, test, CI, manufacturing. Layered, opinionated, with named gaps.
Where AI is actually compressing hardware cycle time today, layer by layer: RTL, place-and-route, DV, PCB, DFM, test authoring, supply.
The stack that lets every test run in CI, not a lab bench: unit, integration, HIL, on-target, and compliance. Where the gaps are.
What validation looks like when specs, tests, coverage, and sign-off artifacts all live in Git. The tools, the formats, the missing layer.
The workflow from idea to shipped unit (requirements, CAD, BOM, MFG, field) and which layers have been code-ified vs which are still PDFs in SharePoint.
hw.dev is operator-led. Software-first view of hardware. Everything-as-code. Shift-left testing. Product realization.
Not a news site. Not an aggregator. An intelligence layer: Signal to read the week, Analysis to read the shift, Stack Maps to read the space.
Future tools may include BOM Intelligence, Test Intelligence, Validation Intelligence, Supply Chain Intelligence, and Product Realization Intelligence. Intelligence is the identity; the tools are the follow-through.