Hardware is catching up to software. hw.dev tracks where that is happening, where it is still broken, and what builders should do about it.
Hardware isn't slow because of physics. It's slow because of coordination, validation, and tooling.
Those constraints are starting to break.
The bottleneck is shifting to decision-making. The teams that win will be the ones that compress the loop:
Short posts on meaningful developments. What happened, why it matters, what it enables, operator read.
Intel is the first foundry to ship HVM logic on High-NA EUV, dual-qualifying specific 18A layers with yields matched to the incumbent NXE platform -- removing the last production-readiness gate on the node.
Quadric's second Series C close brings IFC as lead, funding a general-purpose NPU architecture built to run any inference workload via SDK reprogramming rather than a new tape-out.
TYLsemi emerges from stealth with $43M and the industry's first pre-integrated IO, power, and memory chiplet stack for custom AI XPUs, claiming 50% development time reduction from architecture to HVM.
ASML Q2 results beat guidance at EUR 9.3B revenue, but the decision-relevant number is the capacity plan: 30% more low-NA EUV and DUV immersion tools in 2027, with another 30% under investigation for 2028. That signal sets the ceiling on advanced-node wafer availability for every team planning a 2027-2028 tape-out.
Long-form essays on the shifts reshaping hardware development. What is changing, why now, who benefits, what builders should do.
TYLsemi, JEDEC SPHBM4, and ACCM Celeritas arrived in one week with three independent angles on the same constraint. Chiplet bring-up has not been a BOM problem. It is about to be.
Chiplet economics and AI training scale are making late-stage verification intolerable. The shift from tapeout gate to in-loop constraint is already shipping.
Opinionated, living reference maps of the modern hardware development stack. Layers. Incumbents. Insurgents. Named gaps.
First cut at the layered map of modern hardware development (from design through manufacture) with named incumbents, insurgents, and gaps. Updated as the ground moves.
The end-to-end stack a modern hardware team actually runs on: design, simulation, test, CI, manufacturing. Layered, opinionated, with named gaps.
Where AI is actually compressing hardware cycle time today, layer by layer: RTL, place-and-route, DV, PCB, DFM, test authoring, supply.
The stack that lets every test run in CI, not a lab bench: unit, integration, HIL, on-target, and compliance. Where the gaps are.
What validation looks like when specs, tests, coverage, and sign-off artifacts all live in Git. The tools, the formats, the missing layer.
The workflow from idea to shipped unit (requirements, CAD, BOM, MFG, field) and which layers have been code-ified vs which are still PDFs in SharePoint.
hw.dev is operator-led. Software-first view of hardware. Everything-as-code. Shift-left testing. Product realization.
Not a news site. Not an aggregator. An intelligence layer: Signal to read the week, Analysis to read the shift, Stack Maps to read the space.
Future tools may include BOM Intelligence, Test Intelligence, Validation Intelligence, Supply Chain Intelligence, and Product Realization Intelligence. Intelligence is the identity; the tools are the follow-through.