Hardware is catching up to software. hw.dev tracks where that is happening, where it is still broken, and what builders should do about it.
Hardware isn't slow because of physics. It's slow because of coordination, validation, and tooling.
Those constraints are starting to break.
The bottleneck is shifting to decision-making. The teams that win will be the ones that compress the loop:
Short posts on meaningful developments. What happened, why it matters, what it enables, operator read.
Hardware teams targeting edge AI silicon with autoregressive workload assumptions are designing the wrong memory hierarchy: block-diffusion LLMs have immutable prefix blocks that autoregressive KV-caches cannot exploit, and the co-design penalty is now quantified at 3.8x energy.
HBQ co-designs block quantization with a 28nm ASIC at MICRO 2026, delivering 2.3x area and 4.6x energy efficiency over weight-only quantization at the same accuracy, setting a new baseline for what inference accelerator teams are expected to achieve when they treat quantization and silicon as a joint design problem.
The first SPEC CPU update since 2017 reveals AMD Zen 5 has architectural bottlenecks that only materialize at full-system scale, meaning nine years of silicon characterization methodology was missing real-world behavior.
Report-driven LLM agents identify bottlenecks in heterogeneous chiplet designs directly from execution timelines and resource utilization data, replacing the blind sampling that makes data-driven DSE expensive.
Long-form essays on the shifts reshaping hardware development. What is changing, why now, who benefits, what builders should do.
Three proofs in three weeks close the end-to-end AI design case. The constraint has shifted upstream.
Google's TPU8 split confirms that training and serving optimization no longer share a die
Opinionated, living reference maps of the modern hardware development stack. Layers. Incumbents. Insurgents. Named gaps.
First cut at the layered map of modern hardware development (from design through manufacture) with named incumbents, insurgents, and gaps. Updated as the ground moves.
The end-to-end stack a modern hardware team actually runs on: design, simulation, test, CI, manufacturing. Layered, opinionated, with named gaps.
Where AI is actually compressing hardware cycle time today, layer by layer: RTL, place-and-route, DV, PCB, DFM, test authoring, supply.
The stack that lets every test run in CI, not a lab bench: unit, integration, HIL, on-target, and compliance. Where the gaps are.
What validation looks like when specs, tests, coverage, and sign-off artifacts all live in Git. The tools, the formats, the missing layer.
The workflow from idea to shipped unit (requirements, CAD, BOM, MFG, field) and which layers have been code-ified vs which are still PDFs in SharePoint.
hw.dev is operator-led. Software-first view of hardware. Everything-as-code. Shift-left testing. Product realization.
Not a news site. Not an aggregator. An intelligence layer: Signal to read the week, Analysis to read the shift, Stack Maps to read the space.
Future tools may include BOM Intelligence, Test Intelligence, Validation Intelligence, Supply Chain Intelligence, and Product Realization Intelligence. Intelligence is the identity; the tools are the follow-through.