Analysis
Long-form essays on the shifts reshaping hardware development. Product realization, testing, AI, manufacturing, supply chain, CAD, PLM, ERP, validation. What is changing, why now, who benefits, and what builders should do differently.
The EDA Tool Interface Is the New Bottleneck
Agents can reason about chip design. The tools they need to use were built for humans. That gap is closing, in four incompatible ways.
AI agents now fail at RTL-to-GDS not because models lack hardware reasoning, but because EDA tools expose fragmented interfaces designed for humans. Four vendors are fixing it in incompatible ways, and whoever owns the agent API contract owns the next EDA moat.
The Chiplet Integration Tax Has a Product
TYLsemi, JEDEC SPHBM4, and ACCM Celeritas arrived in one week with three independent angles on the same constraint. Chiplet bring-up has not been a BOM problem. It is about to be.
Three independent moves (a pre-validated UCIe chiplet stack, an organic HBM4 substrate standard, and a CTE-matched material on existing organic lines) arrived in one week. The chiplet integration tax is a coordination problem, not an electrical one, and the first products built to remove it are shipping.
Hardware Verification Moves Into the Loop
Chiplet economics and AI training scale are making late-stage verification intolerable. The shift from tapeout gate to in-loop constraint is already shipping.
Hardware verification is completing the same move software testing made 15 years ago, from a phase at the end of design to a constraint running inside it. The chiplet era is what makes the old model intolerable.
First Silicon Success Is at a 20-Year Low. That Is Why EDA Is Getting Agents.
The verification coordination wall is real, it is getting worse, and the sign-off gate is where the value gets captured.
Synopsys, Siemens, and Cadence all shipped agent interfaces on their sign-off tools in May 2026, the same month autonomous chip design hit production scale. The 14% first-silicon success rate from the 2024 Wilson Research Group study is the baseline that explains why.
RISC-V Passed the OS Gate
The RVA23 profile mandate settled the portability argument that held RISC-V at bay from production embedded Linux
Ubuntu mandating RVA23 as its minimum RISC-V baseline removed the BSP-fork maintenance tax that kept embedded Linux teams on Arm. The portability argument for staying on Arm just got structurally weaker.
Agentic EDA Is Real. The Coordination Problem Moved, Not Solved.
Three vendors shipped multi-agent AI in 30 days. The constraint they removed is internal to their own stacks. The one they didn't remove is the one that costs most teams the most time.
Synopsys, Cadence, and Siemens each shipped multi-agent AI in April-May 2026. Every agent stack works only within its own vendor's tools. The cross-tool coordination problem is intact, and it is the one most teams actually have.
Agents Now Build Production-Class Chips. The EDA Bottleneck Has Moved.
Design Conductor built a full AI accelerator from an arXiv paper in 80 hours. The constraint removed is not design speed, it is the human at every abstraction boundary.
Fully autonomous RTL-to-GDSII agents just crossed from academic exercises to production-class silicon. The constraint removed is not design speed: it is the human at every abstraction boundary, and EDA pricing that assumes one is the first casualty.
The Verification Productivity Gap Is Not a Tool Problem
Why agentic AI is the first architecture that can attack what has always been a coordination problem
RTL verification has been coordination-limited for years, not engine-limited, and agentic AI is the first architecture that attacks the right bottleneck at the cost of per-tool seat licensing.
Hardware is catching up to software
Why hw.dev exists, and what counts as signal here.
The thesis behind hw.dev: hardware development is converging with software development, and the gap is the story. What that means for what we publish, and what we ignore.