Three separate teams published papers this week demonstrating that AI systems can take a hardware specification to verified silicon without human-authored RTL. Architect Labs built and deployed a frontier AI accelerator (Redwood) in under two weeks with no human intervention below the specification level. Jason Hickey's Salt method went from application code to a RISC-V processor tape-out in five weeks using consumer AI subscriptions and a verified Lean 4 compiler, with zero human-reviewed RTL. Ankhdjet lowered a HuggingFace BitNet checkpoint to a via-mask program on SKY130 using an entirely open toolchain, KLayout DRC clean, netgen LVS clean, submitted to fab. Three papers, three abstraction levels, one week. The constraint being removed is not design speed measured in CAD hours. It is human engineers as the mandatory authors of every artifact between a specification and working silicon.
Why the convergence is the signal
Individual proofs of AI-directed design have been appearing for two years. ArchAgent v2, from a joint Google/UC Berkeley/Intel team, entered the 4th Data Prefetching Championship under standard competition rules and won, designing a three-level prefetcher that beat every human entry and outperformed the prior human champion on single-core low-bandwidth configurations. ChipAgents closed a $134M Series A in August with 120 semiconductor companies paying for agentic AI on their design flows and a documented case where 60 hours of human root-cause analysis completed in under an hour. Neither item, read alone, proves the full-stack case. Read together with Redwood, Salt, and Ankhdjet, the pattern is harder to dismiss: AI-directed design has cleared proof-of-concept simultaneously at the accelerator architecture level, the processor level, the ISA extension level, and the inference silicon level, each by a different team using a different approach. Convergent evidence across the whole stack in one week is different in kind from a single lab demo.
Why now and not three years ago
Four enabling conditions converged. LLM code-generation quality crossed a threshold on structured synthesis targets. Generating RTL that also closes timing and passes DRC requires reasoning over multiple constraints simultaneously; that capability was not reliably present before 2025. Formal verification tooling (Lean 4, SymbiYosys, bounded model checking over open solvers) reached the point where automated verification of AI-generated hardware outputs is practical without a human verification engineer reviewing every assertion. The Salt method is explicit: the agents are directed through a verified Lean 4 compiler and executive, meaning the verification step is algorithmic, not manual. Open PDKs (SKY130, GF180) made the full design-to-fab flow executable without commercial tool access, removing the licensing barrier that would otherwise block a one-researcher workflow. And agent coordination frameworks made multi-step flows reliable at a level where end-to-end automation could succeed without human recovery at each stage boundary. Remove any one of the four and the proofs above are not possible.
The constraint being removed
RTL authorship has been the rate-limiting coordination step between a hardware concept and a physical chip for forty years. It required engineers who understood both the intended behavior and the EDA toolchain: what to write, how the synthesizer would interpret it, which timing and DRC constraints to anticipate. That bottleneck created the EDA industry's business model: seat licenses priced against senior-engineer headcount, support contracts priced against the assumption that every customer workflow was an RTL-author problem.
What Redwood, Salt, and Ankhdjet prove, using different approaches, different targets, and different toolchains, is that the authorship bottleneck is breakable at every level of the abstraction hierarchy. The enabling conditions for end-to-end AI-directed design are sufficient across the whole stack, not in one narrow domain.
Who benefits
Software-first teams that want custom inference silicon without building a traditional hardware org are the first beneficiaries. The Salt method is explicit that its design center is one researcher, five weeks, consumer AI subscriptions, with no dedicated ASIC team below the specification level. Hyperscalers with existing silicon programs get leverage: the same headcount can evaluate more designs, tape out faster, and iterate on architectural decisions that previously required months of RTL authorship before getting data. Research groups can now tape out ideas rather than simulate them indefinitely.
Who is exposed
RTL authorship as a standalone job function is the immediate pressure point. The role does not disappear in one product cycle, but the headcount growth trajectory for junior-to-mid RTL authors is now pointing down. The more specific exposure is in EDA vendor pricing. Cadence and Synopsys combined EDA software revenue exceeded $4B in 2025. Both price advanced physical design tools on a model that assumes human engineers are the throughput constraint. If AI agents can run more tool invocations per day than any human team at a fraction of the coordination cost, the per-seat model loses pricing power at the toolchain boundary faster than either company's current roadmap assumes.
What builders should do differently
The hiring question for custom silicon has changed. The constraint is no longer team size. It is specification quality. Both Redwood and Salt made it through to verified hardware; the rate-limiting step in each was the precision and completeness of the specification fed to the AI system, not the engineering headcount below it. If you are evaluating custom silicon in the next 18 months, budget time for specification engineering before RTL team recruitment. A vague specification that would require a human engineer to ask clarifying questions at every artifact boundary will fail an AI system for the same reason it fails a junior engineer.
What could kill this thesis
All three proofs run on open PDKs or academic fabrics. SKY130 is a 130nm process. Moving the same flows to commercial 7nm introduces DRC and LVS complexity that is qualitatively different in scope and in the density of proprietary rule sets. If formal verification at commercial process nodes misses functional bugs at a rate that exceeds what human review would catch, the bottleneck re-emerges at debug rather than creation. The thesis holds only if automated verification scales with automated creation. The three papers above prove creation scales. Verification scaling at production nodes is the open question, and it will remain open until a commercially-fabbed AI-directed design passes qualification. Inside 24 months, either a production chip with no human-authored RTL ships on a commercial node and survives first-pass silicon bring-up, or this argument reverts to lab-scale and the bottleneck re-establishes at debug.