Silicon photonics entered volume production in July, and the EDA stack still cannot verify the full physics of an electro-optical chip. UMC shipped first production wafers for a 1.6T optical interconnect from its 300mm Singapore fab; Tower Semiconductor committed $4 billion to expand silicon photonics capacity in Japan. The Synopsys+Ansys merger, completed the same week, is the first structural response to that gap. The constraint being removed is the vendor boundary between silicon design and physics simulation, which has imposed a manual reconciliation cost on every team doing electro-optical work and blocked the validation loop from closing automatically.
Two Tool Worlds, One Chip
For decades, chip design ran two parallel workflows. Electronic EDA (Synopsys, Cadence, Siemens) handled CMOS design: RTL through synthesis, placement, routing, and signoff. Photonic simulation (Ansys Lumerical FDTD, INTERCONNECT, Zemax) handled optical physics: waveguides, phase, polarization, wavelength, and thermal drift. Both domains are necessary for any chip that moves data optically. Neither tool world speaks the other's language natively.
The kludge connecting them is compact model extraction. A photonics engineer runs a slow, physics-accurate FDTD simulation on a component (a ring modulator, a Mach-Zehnder splitter, a grating coupler), extracts a compact behavioral model from the result, and hands that model to the circuit simulator. At component scale, this works. The approximations are bounded. A single component's compact model is a defensible abstraction.
At system scale, the approximations compound. A co-packaged optics module has hundreds of optical components, each characterized by a compact model extracted under nominal conditions. Thermal coupling between components, wavelength drift under load, crosstalk between waveguides running parallel: none of that is captured in the per-component model. The tool running the system-level simulation has no direct connection to the layout. A change to a waveguide bend radius in the Synopsys flow does not automatically propagate into the Lumerical model. A human does that reconciliation, manually, every iteration. The validation loop for a co-packaged optics design cannot close automatically because the two tool worlds do not share a layout representation: every design change requires a person to carry state between them.
Semiconductor Engineering's deep-dive on electro-optical chip design from July 26 names this directly: photonic behavior is continuous and physics-dependent, not discrete, which makes verification automation difficult. The piece is careful not to say the problem is unsolvable. It says the EDA stack is not there yet for volume production workflows.
Why This Is the Moment
Silicon photonics has been a credible research direction since at least 2012. What changed in 2025-2026 is that AI data center bandwidth demand crossed the copper interconnect limit, and co-packaged optics moved from a roadmap slide to an engineering program at multiple companies simultaneously.
The KV cache bandwidth problem is the proximate driver. Long-context LLM inference is not compute-bound; it is memory-bandwidth-bound. HBM4, near-memory architectures, and CXL-attached memory all attack bandwidth at the DRAM boundary. Co-packaged optics attacks bandwidth at the rack scale, specifically the I/O bandwidth between accelerators and the rest of the system. Both paths are being pursued in parallel because the demand signal is large enough to fund both.
Eliyan's Series C close at a $1B valuation is the data point that marks when this shifted. Eliyan built a die-to-die copper interconnect PHY and sold it into AI accelerators. It is now taking $145M to move into electro-optical interconnects. The strategic investors include Cisco Investments and Lumentum, an optical module manufacturer. When the optical module incumbents lead a round for a die-to-die interconnect company, they are signaling that the two markets are converging within one product generation.
Three years ago, AI silicon teams were not designing electro-optical chips. They were buying transceivers from Coherent, Lumentum, and II-VI and treating optics as a system-level concern, not a chip concern. That boundary is dissolving. The constraint being removed by co-packaged optics is the bandwidth tax on data moving between the silicon package and the rest of the rack. Removing it requires integrating photonics into the chip package, which means photonic design is now a chip team's problem, not a transceiver vendor's problem.
The Vendor Boundary Being Removed
The Synopsys+Ansys combination puts HFSS, Lumerical FDTD, Lumerical INTERCONNECT, and Synopsys's silicon design flows under one organizational roof. The theory is that the vendor boundary between electronic EDA and physics simulation can be eliminated: layout changes propagate automatically into physics simulation, and simulation results feed back into the design closure loop without a human translator.
The first visible artifact is in the Ansys Lumerical INTERCONNECT 2026 R1 release notes: "Synopsys OptoCompiler interoperability." That is not a unified design environment. It is the first interoperability layer between two previously separate tools at two previously separate companies. The endpoint is production-quality co-simulation where a DRC-clean photonic layout is also a verified optical design. The 2026 R1 note is the starting line, not the finish.
The CHIPS Research and Development Office's $874M award to seven companies across integrated photonics, advanced packaging, and memory frames these as a single coordinated R&D problem. The grant framing matters: photonics and compute packaging are not separate industries anymore. They are a shared supply chain, and the US government is treating them accordingly.
Who Benefits, Who Is Exposed
Teams that benefit in the near term are those that have not yet committed to a silicon photonics PDK and tool pairing. The Synopsys+Ansys combination will certify unified design flows for specific process nodes, starting with foundries that already have Synopsys PDK agreements. Foundries offering silicon photonics services (UMC with its 300mm production ramp, Tower with its multi-billion dollar capacity expansion) have clear incentive to be next in line. A team starting a silicon photonics tapeout in H2 2026 will find a unified tool preview available before first silicon comes back.
Teams that are mid-design are in a harder position. They built their compact model libraries against the pre-merger tool stack, with the Lumerical-to-Synopsys handoff baked into their workflow. Migrating those model libraries to a unified environment mid-project is not a setting change. The engineers who ran the FDTD characterization work understand the boundary assumptions; those assumptions need explicit documentation now, before the people who made them move to the next project.
Boutique photonics EDA vendors are the exposed category. Flexcompute's Tidy3D solver competes on FDTD simulation speed and has found a real market in research and early-stage design work. Competing on speed is a different argument than competing on integrated signoff in a production flow, and the Synopsys+Ansys combination is playing the integrated-signoff game. The standalone photonic simulation shop that does not connect natively to a full electronic design flow is being squeezed from above by the merger and from below by the open-source stack.
The Caveat
Two failure modes could stall this. First: tool integration latency. Photonics simulation runs continuous, physics-heavy solvers against continuous geometric structures. Digital EDA runs symbolic operations against discrete netlists. Getting those two computational paradigms to share a layout representation without lossy translation is a harder engineering problem than the merger press release suggests. If the tool teams cannot agree on a common layout model for optical structures within two major releases, the "unified" design environment ships as a shared SKU with two disconnected backends.
Second: the open-source alternative. gdsfactory, DEVSIM, and MEEP have built a photonic EDA stack that is accessible in ways the proprietary alternatives are not: no license server, Python-native, runs in CI. If UMC or Tower publishes a PDK with native gdsfactory support (both have incentive to grow their silicon photonics customer base beyond the Synopsys-certified tier), the lock-in argument for the Synopsys+Ansys stack weakens considerably.
The Synopsys+Ansys unified electro-optical signoff flow has a 12-to-18-month window to ship production-quality unified signoff before that window opens further. If it is not in customer production use by mid-2028, teams designing AI co-packaged optics will find the open-source path the default choice, not a compromise.