Advanced Chip and Circuit Materials (ACCM) shipped Celeritas SMC, a substrate core material that matches silicon's coefficient of thermal expansion (roughly 3 ppm/C) using standard organic laminate manufacturing processes. Vias are drilled with existing mechanical and laser equipment. Build-up films laminate on existing lines. No through-glass vias, no glass-specific metallization steps, no new capital equipment. For package engineers who have been watching glass core roadmaps since 2022 without a credible volume production path, this is the supply-side answer they have been waiting for.
The problem Celeritas SMC solves is specific and geometric. Large-body chiplet packages -- anything above 100mm per side -- generate thermomechanical stress from the CTE mismatch between an organic core at 12-16 ppm/C and silicon at 3 ppm/C. That mismatch drives warpage, bridge-die embedding stress, and interconnect fatigue that packaging engineers cannot route around with design tricks alone. Glass core was the obvious fix: low CTE, high stiffness, low loss. The commercialization barrier was that glass core required wholesale retooling of the substrate supply chain before yield and economics were established. ACCM's claim is that Celeritas SMC delivers the same CTE target on the installed base.
The graded CTE architecture angle is worth attention. ACCM notes that a silicon-matched package core just moves the thermomechanical stress to the board-level interconnect. Their material platform extends to tunable-CTE PCB materials (2-10 ppm/C), which means a designer could grade CTE from die to substrate to board rather than managing a single hard interface. Whether the market moves to graded CTE stacks or settles for glass core on the substrate with conventional PCB underneath depends on cost and yield data that does not exist yet at volume. Packaging engineers evaluating CoWoS-L and embedded-bridge designs should request evaluation panels now; the 100-1200 um thickness range covers most of the interesting constructions.