SemiEngineering's roundup on agentic EDA methodologies is worth reading carefully because it names the structural problem the industry keeps dancing around: the most valuable place to apply AI in chip design -- architecture and verification planning -- is also the place with the least tool support and the most broken data interoperability. Single-tool AI point solutions, which dominated the first wave, sidestep this entirely. Full agentic flows cannot.
The data fragmentation issue is real and underappreciated. RTL, gate-level netlist, SystemC, layout -- each stage produces distinct data types with its own semantics, and there is no settled cross-stage representation that an AI agent can reason over bidirectionally. ESL tools tried to solve this in the 1990s and failed. HLS made partial progress with untimed/approximately-timed models. The AI agentic layer doesn't eliminate this problem; it inherits it. Shift-left only works if you can actually connect the front-end abstraction to back-end physical reality in a way the agent can traverse.
The comment from Siemens EDA is the honest take: agentic flows are proliferating on the functional design side because the degrees of freedom are high and mistakes are cheaper. As you approach tape-out, constraints tighten and the cost of an agent-induced error grows sharply. That's not an argument against agentic EDA -- it's an argument for being very precise about where you deploy it. The companies quietly building proprietary multi-generational design databases as AI training substrates are the ones who will actually close this gap. Everyone else is waiting for standards that may not arrive on a useful timeline.