The long pole in IP delivery was always spec-to-RTL: the weeks of manual RTL authoring, coverage writing, and documentation that sat between a specification and a block a team could actually integrate. AI is removing that pole. The Semiconductor Engineering roundup documents IP developers at Siemens EDA, Cadence, and Arm reporting that AI now drafts RTL, generates test benches, flags coverage gaps, and writes integration docs -- not as experiments but as deployed workflow steps.
The mechanism is not that AI is replacing IP engineers. It is that AI is collapsing the serial handoffs that made IP development slow. Spec-to-RTL used to require a human to hold context across the entire block for weeks. Now the human's job is to set intent, review AI output, and close the gaps AI cannot close: corner cases with physical dependencies, verification of properties that require deep design knowledge to even formulate. The bottleneck has moved from generation to judgment.
What changes downstream: IP discovery and reuse. When every block ships with AI-generated metadata and searchable documentation, the integration friction that kept teams writing new RTL instead of reusing existing IP gets cheaper. The constraint on reuse was never technical -- it was the cost of understanding someone else's IP well enough to trust it. AI-searchable metadata and auto-generated integration guides reduce that cost by an order of magnitude.
The losers are IP vendors whose pricing model assumes high customization cost. If a chip team can adapt and document any block in days instead of weeks, the premium on pre-validated silicon IP with dedicated support staff compresses. ARM, Cadence, and Synopsys have enough scale to absorb this; the mid-tier IP boutiques that charge for integration consulting are the ones exposed over the next 24 months.