The paper's claim that AI designed a PQC chip is the headline. The more important finding is buried underneath: the standard verification gate for PQC silicon has a structural blind spot, and the industry is running it on every accelerator tape-out. Known-answer tests sample fixed seeds that reach only the depths those seeds trigger. ML-DSA's rejection sampling loop executes a data-dependent path each time. A norm-check bug that outpaces block-RAM latency passes every KAT regression while leaving final coefficients unverified. The escape only surfaces at reject-loop iteration 5 -- a depth no fixed-seed KAT will exercise.
The fix is a byte-exact golden-reference oracle paired with randomized adversarial soak. 301,343 data-dependent signings, zero escapes. The oracle doesn't author; it judges artifacts. That distinction is load-bearing: when the verification gate is artifact-based rather than authorship-based, the question "can we trust AI-generated RTL?" becomes answerable by running the gate rather than by auditing the process. The 232 logged LLM experiments that drove ML-KEM-768 and ML-DSA-65 from RTL to silicon are the engineering record; the oracle is what makes that record legible.
NIST PQC migration timelines are published, and silicon that ships with a crypto defect cannot be patched remotely. Every PQC accelerator design team running only KAT regression carries this blind spot today. The paper hands over the tool to close it. Whether it arrived via LLM agent or senior designer is the wrong question to spend time on.