Most AI tools for writing chip logic work by prompting again and again: ask a model for a better version, read what comes back, and repeat. Alpha-RTL, from researchers at the Chinese Academy of Sciences' Institute of Computing Technology, retrains the model itself while it works on a single block. Each rewrite it proposes for a piece of register-transfer level (RTL) code, the hardware description chip designers write before layout, gets simulated, synthesized into gates, and timed. Those results feed straight into an update of the model's weights, so later attempts build on what the tools measured.
The team pointed it at floating-point circuits from the XuanTie C910, an open-source RISC-V processor core. On one 24-bit block, the best design cut area times delay (a combined measure of how big and how slow a circuit is) by 52.8% using the open-source Sky130 cell library, 44.0% with Nangate45, and 35.0% with GF180MCU. What the model found is readable: it replaced one flat 24-way priority check with six smaller groups and reused a cell already in the C910 design. Every reported result is formally proven equivalent to the original, and the measurements come from Yosys and OpenSTA, two open-source tools for synthesis and timing analysis.
It isn't cheap. Each result took 100 training steps on eight GPUs, which is more than anyone will spend on routine cleanup. For teams building design copilots, the useful part is the setup: the model only gets credit for a design that the tools have measured and the equivalence check has passed, however good the code looks.