Venice is in production. AMD confirmed May 21 that its 6th Gen EPYC server CPU is ramping on TSMC 2nm, the first high-performance computing product from any vendor to reach that milestone. This is not a tape-out announcement. Wafers are running.
The mechanism that makes Venice relevant beyond the process-node benchmark is the packaging. AMD is pairing Venice with EFB-based 2.5D packaging (embedded bridge die) in the Helios rack-scale platform alongside MI450X GPUs, targeting multi-gigawatt deployments beginning 2H 2026. EFB bridges enable much higher intra-package interconnect bandwidth than traditional organic substrates, which means the CPU-to-accelerator bandwidth that has been a bottleneck in scale-up AI racks is getting addressed at the packaging layer, not just the silicon layer. AMD also announced Verano, a follow-on EPYC optimized for performance-per-dollar-per-watt with integrated LPDDR, explicitly targeted at agentic AI workloads where memory bandwidth per watt matters more than raw compute throughput.
For teams building or evaluating AI infrastructure for 2027 deployments: 2nm-class server CPUs are in production now, not on a roadmap. The Helios platform with Venice and MI450X is a 2H 2026 product. Any infrastructure architecture assessment that treats 2nm as a 2027-or-later assumption needs to be updated. The vendors whose server roadmaps depend on an extended 3nm window as a differentiation buffer are the ones exposed.