Every analog vision pipeline that feeds an analog accelerator today crosses an ADC/DAC boundary twice: once to digitize sensor output, once to restore analog weights on the other side. That double conversion is not a routing detail. It is the dominant energy and latency cost in the system. Researchers at Illinois have shipped a time-encoded analog photonic interposer that removes it entirely by converting amplitudes into timing intervals, transmitting them over a WDM photonic link, and reconstructing values at the receiver without an explicit high-precision converter pipeline.
The mechanism is an analog-to-time converter (ATC) at the transmit end and a time-domain reconstructor at the receive end, with implicit 6-bit quantization baked into the timing resolution. One wavelength per processing element, independent of bit precision. On the 560x560 Visual Wake Words benchmark the pipeline achieves 2.04x energy-delay product improvement over an 8-bit digital electrical baseline, 89.87% accuracy on ResNet18, and the advantage widens with link length because the photonic channel does not accumulate the per-meter copper loss that kills analog fidelity at multi-chiplet distances.
The constraint being removed is not interconnect bandwidth. It is the assumption that sensor data must become digital before it can be moved. That assumption is load-bearing for every ADC/DAC vendor in the vision pipeline, and for the SoC floor plans that budget die area for converter arrays. A photonic interposer that keeps signals analog across chiplet boundaries reframes where the compute boundary sits: the in-pixel analog compute + photonic link + analog accelerator becomes one continuous pipeline, with no digitization tax between stages. The near-term pressure lands on chiplet co-design workflows that still treat the sensor-to-accelerator handoff as a digital interface contract.