ArchAgent v2, from a joint Google/UC Berkeley/Intel team, entered the 4th Data Prefetching Championship under identical competition rules and won. The autonomously designed three-level prefetcher achieves a 3.8% geometric mean IPC improvement over baseline and a 0.3% improvement over the prior human champion (BertiGO). On single-core low-bandwidth configurations the margin widens to 4.6% vs 2.6% for BertiGO. The search explored 12,000 candidate designs. No human wrote the winning prefetcher.
The earlier ArchAgent worked for single-level cache replacement but did not scale to multi-level prefetching, where the search space is larger and degrees of freedom multiply. v2 adds two mechanisms that make the difference: a cascaded evolutionary search that evolves and freezes prefetchers at each cache level sequentially (avoiding the exponential joint search space), and a hardware-realizability feedback loop that estimates physical size cost in real time and eliminates designs that cannot fit within competition area budgets before they run full simulation. The second mechanism is the more important one. Automated architecture search without hardware feasibility constraints produces academically interesting results that cannot be built. Embedding size estimation into the evolutionary loop is what turns this from a research curiosity into something a chip team can use.
The open problem the paper names honestly is multi-core evolution: simulation latency in multi-core settings currently impedes evolution speed enough that results there remain poor. That constraint is worth watching. Single-core prefetching is a solved problem for automated agents; multi-core is where the real design complexity lives, and it remains human territory for now. The benchmark that matters next is how ArchAgent performs when core-count goes up.