RTL simulation speed is a validation throughput problem, and for AI accelerator designs ARMOR pegs the binding constraint in the right place: not compute, but the CPU front-end. Their profiling found over 50% of pipeline stalls in state-of-the-art simulators come from instruction cache overflow caused by fully unrolling the RTL graph into per-node instruction sequences. The fix is node compression -- packing multiple structurally isomorphic nodes into a single instruction sequence using bit-level data parallelism. The result is 1.6x speedup on CPU designs and 2.7x on AI accelerators, accepted at MICRO 2026.
The mechanism is what makes this interesting. ARMOR uses two passes: first a module-aware isomorphic subgraph identification that finds compression candidates across module instances (exploiting the fact that the same sub-circuit appears hundreds of times in a large design), then an alignment-aware dense packing strategy that groups nodes according to dataflow dependencies while preserving data reuse. The bit-level parallelism scheme then executes compressed node packs with a single instruction sequence instead of one per node, reducing code footprint without giving up the optimization benefits of a fully unrolled graph.
The practical implication is more simulation iterations per hour for teams verifying AI accelerators, which are the designs where fast simulation matters most and where current tools are slowest. Simulation throughput sets a ceiling on how many RTL variants a team can actually evaluate before tapeout. A 2.7x speedup on AI accelerator designs does not change what simulation can check, but it moves the answer to "how many design alternatives can we afford to run" by a meaningful factor. Teams relying on commercial RTL simulators priced per CPU-core-hour will find ARMOR's open approach cuts cost by more than it cuts runtime.