Arteris sells network-on-chip IP. Revenue up 39% year-over-year, annual contract value plus royalties at a record $92.8M, trailing-twelve-month royalties up 67%. That is not a company finding growth at the margins of a crowded category; that is a category whose demand is accelerating faster than in-house design teams can absorb.
The mechanism is chiplet complexity. When a chip is a single die, a custom bus fabric is tractable (one team, one design, one validation pass). When a chip is multiple chiplets with heterogeneous interconnect, high-bandwidth memory, functional-safety requirements, and AI inference workloads, the interconnect design space explodes. The coordination problem inside the chip mirrors the one outside it: more interfaces, more protocols, more timing domains, more power management interactions. Arteris's FlexGen smart NoC IP and Magillem SoC integration automation are selling because teams are hitting the limit of what they can hand-route and hand-validate. Key Q1 wins include a leading HBM supplier using Arteris to accelerate HBM chip development, a leading hyperscaler licensing the security IP module, and Renesas deploying Arteris on R-Car Gen 5 for ADAS. The MIPS collaboration to accelerate physical AI solutions adds a third design dimension that was not in play two years ago.
39% revenue growth at a pure-play interconnect IP company is a leading indicator, not a lagging one. It means the chip teams signing these deals have already decided that NoC design is not their core competency. That decision, made early in a program, changes what the SoC looks like: fewer custom bus architectures, more parameterized IP, more budget for verification of the interconnect rather than design of it. Vendors still pitching hand-rolled fabric as a competitive advantage have a shrinking window before the argument stops landing.