Arteris, BAE Systems, and SiFive are turning third-party IP trust into a verification workflow. A new $3.3 million expansion of the Trusted and Assured Microelectronics program funds a repeatable method for evaluating commercial IP inside mission-critical SoCs. The constraint is not finding another security checklist. It is carrying evidence from an IP block through subsystem and chip integration without losing traceability.
Arteris uses a Common Weakness Enumeration-based framework that links hardware weaknesses to requirements, properties, and granular verification evidence. The program applies that evidence chain from IP blocks through chiplets and integrated SoCs running software workloads. Integrators get a coverage-oriented record of what was checked and how, rather than a supplier assertion that has to be reinterpreted at every boundary.
The first useful output should be a reusable assurance package that survives integration into more than one SoC by the end of 2027. Aerospace and defense teams should measure how many manual security reviews disappear when evidence travels with the IP. Vendors that cannot ship traceable assurance data with a block will become the integration bottleneck.