High-NA EUV works. The question TSMC customers answered at the 2026 Technology Symposium is whether it works well enough to justify what it costs, and the answer is no.
The physics case for High-NA is clear: moving numerical aperture from 0.33 to 0.55 shrinks pattern pitch, enabling the transistor densities that 1.4nm and below require. The manufacturing case breaks at three joints. First, the higher NA reduces depth of focus, which means wafers must stay nearly flat during exposure; nanometer-scale topography variation or thermal drift creates defect clusters that conventional process control cannot fix. Second, thinner photoresists required by the narrower focus window absorb fewer EUV photons, amplifying stochastic defects (broken lines, missing holes, edge roughness) in a regime where a handful of random defects can scrap a die entirely. Third, pellicle materials (the thin membranes that protect masks from contamination) are not yet rated for the sustained source power that High-NA throughput demands. New materials are in development; none are production-qualified. Intel had planned High-NA for 14A under Pat Gelsinger. Under Lip-Bu Tan, customer input on process decisions is growing, and Intel customers are watching TSMC's calculus closely.
For fabless teams, the roadmap implication is concrete. TSMC will not require High-NA EUV to deliver N2 or early A14 volume. That means the node economics teams are modeling today (yield assumptions, capex recovery curves, PDK timelines) do not need to price in High-NA risk for the next two to three years. EDA tools supporting High-NA mask writing, inspection, and OPC are also not production-qualified, so design flows betting on High-NA PDKs are betting ahead of available data. The winner in the near term is any team on a conventional EUV scaling path: the 1.4nm gate is not moving sooner than the roadmaps imply. The loser is any EDA vendor whose High-NA tool bets were priced into a 2027 volume ramp.