BigPower skips the simulation step in pre-silicon power analysis. Given RTL source and workload context, an LLM-based surrogate model estimates module-level power for each CPU component without generating switching activity files or running a chip simulation. Demonstrated on the XiangShan RISC-V processor, an open-source high-performance design with production-level complexity.
The standard pre-silicon power workflow is sequential: write RTL, run simulation to capture switching activity, feed that into a power tool, read the module-level breakdown. The simulation step is the bottleneck. A full-chip RTL simulation on a large design runs for hours on shared compute that is a constrained resource. Power analysis lands late and rarely because the simulation cost makes early exploration impractical. BigPower trains on source-level design attributes (architectural hierarchy, module connectivity, configuration parameters, workload fingerprint) and produces the per-module power breakdown directly. The RTL is the input. The simulation is not.
XiangShan matters as a test case because it is not a toy. It is a superscalar, out-of-order RISC-V design used as a reference implementation in both academic and pre-production silicon projects. BigPower's results hold across diverse configurations and workloads on real design data. The simulation path is not eliminated for final sign-off, and nobody should confuse this for a signoff tool. But the early-phase exploration loop (microarchitecture tradeoffs, frequency target selection, clock domain partitioning) now has a fast source-level path that does not touch a simulation slot. Teams doing design space exploration at scale will compress that loop by a meaningful factor. The named loser is the simulation-first culture that has kept power analysis a once-a-week gating event rather than a per-commit check.