Meta and Broadcom signed a multiyear, multigenerational agreement running through 2029 to co-develop Meta's Training and Inference Accelerator (MTIA) chip line. The immediate deliverable is what both companies are calling the industry's first 2nm AI compute accelerator. The Broadcom XPU platform handles logic, memory, and high-speed I/O co-design across generations. Meta's stated goal is deploying more than 1 gigawatt of custom silicon -- a unit of measure that translates directly to data center power contracts, not just chip counts.
The technical signal here is the process node. 2nm ASIC deployment ahead of comparable GPU products reflects how much TSMC priority the hyperscalers have accumulated. NVIDIA's Blackwell is on 4nm. TSMC's 2nm node (N2) is ramping for late 2025 through 2026, and the hyperscaler ASICs are apparently first in line ahead of the GPU roadmap for that node. Broadcom's advantage in this deal is exactly its XPU platform -- a packaging and I/O architecture that allows Meta to change the compute die across generations while keeping the memory and I/O layer stable, which cuts NRE on successive MTIA chips.
The longer-term read is about what multigenerational commitment means for ASIC economics. The complaint against custom silicon has always been the NRE amortization problem -- you spend $300M on a chip that is obsolete in 18 months. The Broadcom-Meta structure solves this by sharing a platform across generations, the same way Apple Silicon generations share package form factors and memory interfaces. Each generation the NRE is smaller relative to the deployed base. At 1 gigawatt and growing, Meta's custom silicon has reached the scale where this pencils out decisively against merchant GPU procurement -- and the Broadcom partnership locks in that advantage through 2029 at minimum.