The paper reports an honest negative result: on an 8GB edge board running Qwen3-30B-A3B at 4-bit (18GB model), expert prefetch delivers zero throughput benefit and the trace-driven oracle actually makes things worse. The constraint is not locality or predictability. It is byte volume over a saturated eMMC bus, and prefetch cannot reduce byte volume. The fix that works is quantizing down until the model fits a 16GB unified-memory device, which takes decode from pinned-at-eMMC-ceiling to 11.5 tok/s GPU-resident -- a 22x improvement from a tier change, not from a smarter scheduler.
The framework behind this is worth keeping. The authors define an address-determinism taxonomy (A0 through A3) classifying each parameter group by when its fetch address is known during a forward pass. This converts MoE expert prefetch scheduling into a single-machine feasibility problem with release times, yielding a closed-form windowed roofline. The framework also predicts where prefetch does work: on an A100 with PCIe offload, where the fast tier caches most of the model and per-token transfer is close to compute time. Predictability (91.2% routing prediction from pre-attention state on Qwen3-30B) is a real property; it just does not convert to throughput when the bus is the bottleneck.
The practical read for teams building edge LLM hardware: the hardware selection decision is often being made with the wrong proxy. Maximizing storage speed while undersizing the fast tier is the wrong optimization. The roofline makes the transition point calculable -- the team that embeds this into their hardware DSE eliminates a class of expensive prototype-and-measure cycles. Teams shipping inference appliances in 2026 should run the bytes-per-token math before speccing the storage controller.