Chip-design agents have been graded on the part of the job that looks most like software: turn a specification into RTL and pass a testbench. Build-A-Chip-Bench moves the hard gate to the end of the flow. An agent must produce a routed GDS that passes hidden functional tests, hold timing, DRC, and routability before power, performance, and area count for anything.
The benchmark spans 12 steps from workload definition through physical verification, using open-source tools and an open PDK. That exposes the feedback loops point tests miss. A congestion problem can force a floorplan change. A timing failure can invalidate a microarchitecture choice made hours earlier. The best tested agent passed the hard gate on 65% of tasks but scored only 16.6% overall, with weak planning around slow tool runs and poor recovery when downstream evidence contradicted an earlier decision.
EDA agent vendors should publish Build-A-Chip-Bench results before asking for production access. Passing VerilogEval proves code generation. Passing this benchmark proves the agent can preserve correctness while making physical tradeoffs, which is the minimum evidence a tapeout team should accept in 2027.