Intel 18A is in production on Xeon 6+. 14A is the node after that, and Cadence is now in a multi-year design technology co-optimization agreement to build 14A PDKs alongside Intel Foundry's process development. DTCO at this stage means the EDA toolchain and the manufacturing process tune together before the node freezes. That is different from what happened with 18A, where EDA readiness lagged process readiness by a meaningful margin.
The mechanism matters. PDKs built through DTCO capture real parasitic data, DRC/LVS rules, and timing models from process measurements, not estimates. Cadence timing, power, and physical tools run against actual 14A design rules as the process matures. Teams that engage early get design feedback before tape-out decisions, not a surprise after sign-off. The multi-year framing signals that Intel is not expecting 14A to be production-ready in quarters; this is a sustained co-development commitment, not a standard reference flow agreement.
The barrier to going first on a new foundry node has historically been EDA readiness. Intel 18A had that problem; the PDK and tool support lagged. The Cadence 14A DTCO agreement is Intel Foundry's visible corrective action. For fabless teams evaluating Intel Foundry against TSMC N2P for a 2028-2029 tape-out, EDA readiness just shifted from a known liability to a stated commitment. Teams that want to be in the co-optimization loop should engage with Cadence and Intel Foundry now. The teams exploring 14A design starts today will have an 18-month lead on teams waiting for a "stable" PDK.