Agentic AI has been steadily eating the digital EDA stack for 18 months. RTL generation, formal verification, place-and-route closure: all credible automation targets now. Analog has held out. Analog circuit design depends on seasoned engineers reading parasitics, cross-corner behavior, and layout sensitivities that do not reduce to a prompt or a cost function. Cadence's ViraStack is the first commercially announced agentic AI agent targeting this workflow directly, with early customers reporting 3-10x productivity on design migration between process nodes.
The mechanism is process node migration, not greenfield analog design. That is a deliberate scope choice. Migration is well-defined: a known schematic, a target PDK, a set of performance specs that must be met on the new node. The constraints are enumerable even if the solution space is large. ViraStack automates the schematic re-targeting, the sizing iterations, and the corner verification loops that currently require a senior analog engineer to supervise by hand. The company claims fully autonomous migration on tested circuits. That is a meaningful claim, not a demo.
The consequence is not that analog engineers are displaced. It is that the migration tax -- the 6-12 months a team currently spends porting a mature analog design to a new node -- shrinks to weeks. That changes the economics of analog IP reuse across generations. Teams that have been avoiding node migrations because the porting cost ate the performance benefit now have a reason to recalculate. The vendors most exposed are the boutique analog IP houses whose value proposition rests on the cost and difficulty of that migration work. ViraStack does not make analog design easy. It makes the transition between nodes cheaper, which is where most of the economic friction was sitting.