All four leading fabs are building toward CFET production, and the interconnect decisions they are locking in now are architectural, not just process. Intel, Samsung, TSMC, and IBM have converged on direct backside vias for power delivery. The open variable is how the n-type and p-type transistor tiers connect to each other and to front-end wiring. Material choice (epitaxy quality, gate dielectric stack, workfunction metal selection) and via pitch at the inter-tier interface vary by fab, and each choice locks in an integration path that does not survive a foundry switch.
What is shifting: TCAD-based virtual simulation is now doing the integration work that previously required a split-lot silicon run. The simulation sweep that used to take six months of fab time now runs in two weeks. Virtual simulation is not a substitute for silicon verification, but it is the primary pathfinding tool for CFET integration decisions, compressing the gate stack and interconnect decision loop before any wafer loads. That is a concrete 10x reduction in the design-to-process-PDK handoff cycle.
The consequence for design teams: foundry selection for CFET-era products is an architectural decision. The integration path your fab commits to constrains back-end wiring strategy, inter-tier capacitance budgets, and timing closure in ways that do not cross fab boundaries. Teams that are already running TCAD process simulations against the CFET parameters their target fab publishes will close CFET tapeouts on schedule. Teams waiting for a production PDK to start pathfinding are ceding 12-24 months of integration learning to the ones that are not.