Chip Design Learning added Python testbenches for five small chip designs and runs all of them on every push. The tests use cocotb, a library that lets Python drive and inspect a Verilog simulation, so a filter can be checked against the same Python code that created its coefficients instead of a second handwritten copy of the math.
The strongest part is the mutation check. The project deliberately breaks its register-transfer-level (RTL) hardware descriptions, then records which tests notice. A random pulse-width modulation test catches a bug that every constant-duty test misses, while filter tests catch changed coefficients, bad saturation, and incorrect rounding. The full set takes about 10 seconds in continuous integration (CI), and a failed run leaves machine-readable test results.
This is a useful pattern for teams adopting AI-written hardware: grade the testbench by the defects it rejects, not by its line count or coverage report. Start with one bug from a recent review, plant it again, and require the automated test to fail before trusting that test as a release gate.