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SignalEE Times

Chip Sovereignty Has Moved Past Chips -- AMD CTO on the System-Level Shift

AMD CTO Mark Papermaster and Chip War author Chris Miller argue that semiconductor strategic value has shifted from fab ownership to system architecture -- AI accelerators, advanced packaging, memory bandwidth, and the software stack that ties them together.

#ai-hardware#chiplets#semiconductor#trends
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AMD CTO Mark Papermaster's framing is worth quoting directly: "The way people think about strategic leadership in AI has really changed as compared to just a year ago. AI used to be thought of as associated with a GPU. But over the last year, it's become clear that you need extensive computation across a much broader system." EE Times interviewed Papermaster and Chip War author Chris Miller for a piece on why chip sovereignty policy is chasing the wrong metric.

The argument is straightforward and correct. Governments have poured tens of billions into semiconductor manufacturing subsidies under the assumption that controlling fabs equals controlling AI. That framing made sense in 2020. It doesn't capture 2026. The differentiating layer has moved: AI accelerators, high-performance CPUs, advanced packaging, memory bandwidth, and the software stack are now where the strategic value is created. A country that controls a leading-edge fab but not the chiplet interconnect architecture, the HBM supply chain, or the training software is not strategically independent.

Papermaster's description of agentic AI workloads is the concrete version of this: workloads that orchestrate CRM, ERP, databases, GPUs, and accelerators simultaneously require heterogeneous compute across the full system. The bottleneck shifts by workload. Chiplet architectures -- which AMD pioneered and the industry has adopted -- exist precisely to handle this: break the die into optimized components, combine at package level, adapt to application requirements. Advanced packaging is now the integration layer that determines performance, power, and yield. Chris Miller points to packaging as one of several areas whose strategic importance has risen alongside AI.

The uncomfortable implication for hardware engineers: if you're designing systems for 2027 and beyond, fab geography is less relevant to your supply chain risk than packaging supply concentration (mostly TSMC/ASE), HBM allocation (Samsung/SK Hynix/Micron), and chiplet interconnect standards. Those are the actual bottlenecks. The policy frameworks haven't caught up yet, but Papermaster and Miller are sketching the map.