Compute-in-memory research has treated the interconnect between processing elements as inert bus fabric. CHIPSMORE, from the National University of Singapore, challenges that assumption by making the interconnect itself programmable compute. The Inter-PE Computational Network (IPCN) has its own ISA, a configuration co-processor, and unit routers, which means operator-level computation (reductions, activations, data movement transformations) can happen in the network rather than in the memory cells or outside chiplet. The result is a single chiplet architecture that handles base LLM inference, LoRA adaptation, long-context KV cache, and batched multi-request workloads without rebuilding the chip for each mode.
The memory subsystem is composable rather than fixed: router scratchpad, SRAM-DCIM (digital CIM), and embedded DRAM are allocated dynamically per workload via a hierarchical KV scheme. RRAM-ACIM (analog CIM) handles weight-stationary matrix multiply; SRAM-DCIM handles activation-stationary paths. The non-replicated multi-request pipeline runs concurrent requests through a single weight copy, eliminating the per-request replication overhead that limits batching efficiency on most CIM accelerators.
The conventional CIM design assumption is that moving compute closer to memory is the full optimization. CHIPSMORE points to the next constraint: the interconnect between CIM tiles. When the interconnect cannot compute, every reduction or data transformation crosses chiplet boundaries twice. Moving even a fraction of that work into the network cuts traffic volume and latency. The architecture makes fixed-interconnect CIM chiplets a weaker baseline within the next generation of inference hardware.