The ADC/DAC conversion tax in compute-in-memory accelerators is well-documented: analog score voltages cross the analog-digital boundary to run softmax in the digital domain, then cross back. This paper removes the crossing. The circuit uses a shared falling ramp to convert each input score into a time-domain event, generates an exponential weight via RC decay, and normalizes in-circuit, all without an intermediate ADC. The key architectural property is that the softmax temperature (which governs attention sharpness) is programmable through the ramp slope and RC time constant, not through transistor weak-inversion characteristics -- which are process- and temperature-dependent and hard to control reliably.
The implementation runs 128 elements simultaneously in GlobalFoundries 22nm FDSOI, occupies 9453 um2 including shared ramp circuitry, and achieves 25.5 pJ per output element at 242.97 ns latency. Post-layout extraction results include Monte Carlo analysis across process, temperature, and mismatch. The circuit achieves 24.46 mV RMSE versus ideal softmax. The authors close the loop by feeding the extracted characteristics into a MemTorch-based hardware-aware Transformer, where validation loss lands within 2.5% of the ideal-softmax baseline.
The signal here is not just the circuit. It is that the programmable-temperature knob is implemented without process-dependent nonlinearities, which has been the reliability barrier for analog softmax in production. Most analog ML circuits trade programmability for energy efficiency, then fail qualification because the process variation makes the trade unpredictable. A ramp-slope/RC control point is a geometric parameter, not a device physics parameter. If the RMSE and process-variation results hold at larger arrays, the main remaining blocker for CIM transformers in real silicon is not the exponentiation -- it is the normalization at scale.