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SignalarXiv

ContractHIL-HLS Closes the HLS Loop to Board-Level With Hardware-in-the-Loop Feedback

A multi-agent HLS workflow that feeds Vivado build output and PYNQ runtime measurements back into code generation reaches 70.4% pass@1 on HLS-Eval and closes to board-level, not just RTL.

#eda#tools#fpga#verification#ai-hardware
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Every LLM-assisted HLS paper so far has stopped at the RTL or kernel boundary. ContractHIL-HLS extends the feedback loop to the board: agents compile with Vivado, flash to PYNQ, measure runtime and power, and feed those measurements back into the next generation cycle. The gap being closed is not code quality. It is the gap between a kernel that passes simulation and a design that runs on hardware.

The architecture is three agents. A Contract Agent converts natural language requirements into a structured specification with explicit interfaces, constraints, and rollback rules. An HTML Agent renders that contract as persistent structured state. A Hardware-in-the-Loop Agent implements the design and revises it against measured evidence from the physical board. On 94 HLS-Eval benchmark tasks, the structured contract alone improves single-sample pass rate from 64.0% to 70.2%. The full flow with HIL feedback reaches 70.4% pass@1 and 76.6% pass@5.

The interesting structural choice is the contract as a semantic artifact rather than as a prompt. Requirements become explicit typed objects with rollback rules, not conversational context that drifts across iterations. That design gives the agent a ground truth to check against after each hardware measurement, which is the missing mechanism in most agentic HLS work.

The practical ceiling today is PYNQ-class hardware and the HLS-Eval task set. Neither represents the complexity of a production FPGA design. But the pattern, natural language to verified hardware via a contract-grounded multi-agent loop with physical measurement feedback, is the right abstraction. Teams doing HLS at any scale should read this before their next toolchain review.