The scale-up boundary just moved. Copper-based scale-up (the assumption that all GPUs in a tightly coupled domain live within one rack and communicate over copper) is extending beyond the rack as cluster sizes push past the bandwidth limits of copper at those distances. Optical interconnects are entering scale-up, not just scale-out, and optical circuit switching is spreading from Google (where it first powered Jupiter at scale) to other hyperscalers. The emerging term "scale-in" describes compute density within a single server board, which signals that the taxonomy itself is being rebuilt from scratch.
The hardware design implication is in co-design. System-level assumptions about latency, bandwidth, and link budget now require photonic modeling that most digital design flows do not include. EDA tools have been adding silicon photonics support since the mid-2020s, but the gap between "photonics is in the tool" and "photonics is routinely co-simulated with the digital path" is still measured in years of engineering work per team. Optical circuit switching adds another layer: the network fabric is no longer a fixed topology. It is a programmable resource with reconfiguration latency on the order of microseconds, which changes how you model worst-case communication patterns.
For teams designing silicon or systems for AI inference at scale, the architectural assumptions -- terabits per second per package, link distance, topology -- are being written by hyperscalers and will be codified into OCP specs inside two years. Accelerators that ship without optical interconnect on the roadmap will be designed for a topology the market is leaving behind. The window to get photonics into the co-design process is inside the next two design cycles.