Google's Coral neural processing unit (NPU) project added a software test that writes alternating bit patterns through the processor's local data memory and external memory port, then reads the data back. It also reads every word of instruction memory after the simulator fills unused locations with known patterns. This is a wiring test disguised as a tiny program, and it can expose stuck or disconnected bits before anyone has a chip on a bench.
The same workload runs on the base core and the vector-enabled core through Cocotb, a Python framework that drives hardware simulations. Alternating all zeroes and ones forces every data bit to change state, while the full address sweep exercises the paths that choose each memory location. Because software initiates the traffic, the test covers the processor, memory blocks, and the Advanced eXtensible Interface (AXI) that connects external memory as one system.
This test won't prove that memory meets timing on silicon, but it should become a gate for every core configuration now. A memory option that can't run this sweep in simulation shouldn't be allowed to consume a field-programmable gate array build or a lab slot.