Google's Coral neural processing unit (NPU) project has moved its workload tests onto CoralFlow, one test runner that can target Verilator, Synopsys's commercial chip simulator, a software model, or a field-programmable gate array (FPGA) board. The same Python test now follows a chip feature from a fast local simulation to real hardware without being rewritten for each environment.
The change is large because the old split had spread through the project. Google migrated vector instructions, Gemma model kernels, LiteRT Micro workloads, and fault tests, then deleted three legacy regression programs and two standalone board runners. CoralFlow supplies one fixture interface for loading a program, writing memory, running to a halt, and reading results. It also filters individual cases and splits them across build workers. Google says sharing compiled models cuts compilations for the Synopsys simulator in half and limits memory pressure in continuous integration.
Shared tests make disagreements between backends useful evidence instead of maintenance noise. A failure that appears only on the FPGA now points toward implementation or timing, while a failure everywhere points toward the workload or architecture. We expect more open chip projects to organize tests around behavior first and treat each simulator or board as a replaceable execution target.