Skip to content
hw.dev
hw.dev/signal/design-conductor-risc-v-ai-cpu
SignalIEEE Spectrum

AI Agent Designs a Complete RISC-V CPU Core in 12 Hours

Verkor.io's Design Conductor agentic AI system produced a verified 1.48 GHz RISC-V core from a 219-word spec -- the first end-to-end autonomous CPU design from spec to GDSII layout.

Thesis connection
iteration velocitytooling

Collapses spec-to-GDSII on a straightforward RISC-V core from a team-quarter to 12 unattended hours, which is the full idea-to-validation-to-layout loop running end-to-end without a human in the middle.

#risc-v#eda#ai-hardware#tools
Read Original

Verkor.io's Design Conductor system took a 219-word requirements document and produced VerCore: a five-stage, single-issue, in-order RISC-V pipeline that meets timing at 1.48 GHz on the ASAP7 7nm PDK, scores 3,261 on CoreMark, and boots uCLinux in simulation -- all in 12 hours with no human intervention beyond writing the spec.

The technical detail worth sitting with: Design Conductor is not a single model doing free-form generation. It is a structured harness that forces LLMs through the same workflow phases a human team would follow -- specification analysis, RTL authoring, simulation, debugging, and layout. The agentic framing matters because it surfaces a real constraint: the system can get stuck in unproductive debugging loops that an experienced engineer would short-circuit in minutes. Autonomous does not mean efficient, and Verkor is honest about that.

What this signals for EDA is less about job displacement and more about where the floor is moving. If a 219-word prompt can produce a simulation-verified, layout-ready 1.5 GHz core, the cost of first-pass RTL has effectively collapsed for a class of straightforward microarchitectures. The interesting constraint is no longer "can AI write RTL" -- it is whether the output can clear physical verification and tapeout DRC on real process nodes. Verkor plans to release VerCore's RTL and build scripts by the end of April and demo an FPGA implementation at DAC. That is the next milestone worth watching.

Back to Signal