Most chiplet simulation today models inter-die links as a fixed latency and moves on. DICE shows that this is wrong in a way that matters: when you include actual PHY behavior (signal-to-noise variation, clock jitter, crosstalk, forward error correction decode latency, and packet retransmissions), the IPC numbers shift. The implication is that teams designing AI chiplet SoCs are running architectural exploration against benchmarks that do not reflect the link behavior their silicon will exhibit.
The mechanism is straightforward. As chiplet designs push bandwidth density higher, the short-reach links between dies get pushed toward their signal-integrity limits. FEC becomes necessary. FEC has non-deterministic decode latency depending on bit error rate. When LLC misses cross a chiplet boundary and hit a retransmission cycle, the resulting stall is not captured by a fixed-latency model. DICE builds a simulator that models all of this end-to-end and shows the delta between simplified and detailed models in IPC across a set of workloads.
The practical consequence lands on any team doing DSE for a chiplet-based AI system. If your simulation infrastructure uses simplified inter-chiplet timing, your workload sensitivity analysis is probably wrong for memory-bound or bandwidth-limited kernels. The error grows as you push toward higher bandwidth density, which is the direction every AI inference chiplet is heading.
Given that UCIe and HBM-based chiplet stacks are now in volume production, the industry has about 18 months before this gap between simulation and silicon becomes a first-class reliability complaint, not an academic finding.