FPGA-based interconnect debugging has had a structural problem: to change what you are tracing, you reprogram the FPGA, which takes minutes, interrupts operation, and cannot catch rare or transient events. Dryas removes that constraint. The paper presents an open-source overlay engine that runs on top of a 30 GiB/s, 200ns FPGA interconnect implementation and lets engineers change trace filters in under a second at full operation speed. The filter change does not require reprogramming the FPGA or interfering with the running interconnect.
The mechanism is an NFA-based overlay: non-deterministic finite automata implemented using state transition elements (STEs) that filter trace events at cache-line granularity. The design uses minimal hardware resources, which means the tracing engine coexists with the interconnect implementation rather than competing with it for LUT capacity. The practical implication is that the debug loop moves from "reprogram, wait, miss the event" to "change filter, observe, iterate." For teams implementing high-speed protocols on FPGAs, this is the difference between a static probe and a live programmable analysis plane.
Dryas is open source and was developed alongside an actual interconnect implementation, not as a standalone tool. That origin matters: the design decisions reflect the constraints of a real system running at 30 GiB/s, not a research artifact. Teams debugging PCIe, CXL, or custom high-bandwidth fabric implementations on FPGAs now have an open baseline for runtime-reprogrammable interconnect tracing that does not require a logic analyzer budget or a full FPGA reprogram cycle.