Every matrix multiply in a neural network training pass routes reductions through an accumulator. If that accumulator is a serial FP32 adder, you hit a ceiling of roughly 2 FLOP/cycle regardless of how wide the systolic array behind it is. DTX names this constraint explicitly and removes it: every reduction is a pipelined binary tree, every FP operator a two-stage pipeline with initiation interval 1. An 8x8 weight-stationary systolic array, fused bias/activation/cast, an 8-lane vector unit, an 8-lane AdamW optimizer pipeline, and a pipelined Gaussian source are co-issued in a 4-slot VLIW. The result is 216 FLOP/cycle, roughly 108x the loop-carried floor.
The verification approach is the part worth studying separately. Without canonical summation order, bit-exact reproducibility breaks. DTX handles this with tolerance-based correctness plus exact-equality carve-outs for cases that require it, and a formally bounded error model. 17 test cases passed across 107,108 elements. One premise-violating program measured 5,340x over budget and was flagged correctly. That is a deliberately engineered correctness regime, not a hand-wave. The authors wrote a verifier, not just a test harness.
The consequence for training silicon design: the standard justification for making systolic arrays larger is that utilization drag from accumulator bottlenecks means you need more parallelism to compensate. If you remove the drag, the economic case for large sparse arrays versus smaller dense arrays changes. This also means any training pipeline that assumes bit-level cross-run reproducibility needs to account for the fact that this architecture pattern is incompatible with that assumption by design. Plan accordingly before it shows up in next-generation training accelerator silicon.