TSMC held its 2026 North America Technology Symposium on April 22 in Santa Clara, announcing A13 technology targeting 2029 production, A12 with Super Power Rail, and TSMC-COUPE co-packaged optics scaling to 14-reticle integration. Synopsys, Cadence, and Siemens each used the event to announce certification milestones on N3, N2, A16, and A14 nodes.
The Cadence number to note: 7% better placed area on 2nm designs via AI-assisted placement, and 2x to 2.5x improvement in logic simulation. Six months ago that kind of per-node claim would have been unverifiable without a tape-out. The fact that Cadence can quote it against a specific node means AI-in-the-loop EDA flows have matured enough to produce repeatable, comparable measurements. That is the shift -- not that AI is being added to EDA, but that AI EDA is now producing benchmarks, not demos.
The Synopsys COUPE disclosure is the more structural signal. Synopsys certified "224G IP for co-packaged optical Ethernet and UALink" on TSMC N2P -- that is the chip-side interconnect IP for co-packaged optics. Most of the COUPE discussion focuses on the optical integration side. The silicon constraint is the interface between die and photonics, and Synopsys certifying that IP on N2P is the step that unblocks actual design starts. Without the EDA IP, the packaging architecture is a roadmap slide.
The A13 (2029) announcement is the structural mechanism that makes EDA incumbency harder to displace than it looks. All three major vendors are now committing to certify flows on nodes that will not produce first silicon for three years. That is not just IP development -- it is PDK integration, multi-physics co-simulation, and DRC/LVS sign-off on a process that will evolve. A new EDA entrant who wants to compete at A14 production in 2028 has to start certification work today. The window for catching the current class of certified vendors is narrow and closing.