An Efinix board project turned its routed Low-Power Double Data Rate 4 memory interface into an open signal-integrity test, then tried to make the test fail. The suite covers all 56 routed nets at 2,800 and 3,200 million transfers per second, across typical, minimum, and maximum device models. It found one real exception: a clock-enable line exceeded its peak-voltage limit by 16 millivolts at the fastest maximum-voltage case, and changing the field-programmable gate array's drive setting fixed it.
The useful part is the deliberate damage. With on-die termination, the resistance inside a chip that absorbs reflections, disabled on one data line, the checker reported a negative 30-picosecond timing margin. Making every trace four times longer still left a 259-millivolt eye opening when termination was enabled; turning it off closed the eye completely. Those failures show that a green result isn't just a permissive script.
The model still uses a substitute memory-chip model and a Texas Instruments input mask because the exact vendor data isn't public. That keeps this from being fabrication approval. If you build a similar pre-layout or routed-board check, copy the failure injection first. A simulation that can't reject a knowingly broken channel shouldn't influence a board order.