Fire Core Nano now runs one compiled program against four versions of a tiny RISC-V processor. The same 5,067 retired instructions take 17,699 cycles on the field-programmable gate array (FPGA) core. The application-specific integrated circuit (ASIC) version takes 35,426 cycles, while a bit-serial comparison core takes 289,979.
The benchmark wraps six small C kernels with writes to a simulation register. A shared testbench counts clock cycles and retired instructions between those writes, so none of the processors needs a built-in performance counter. The program checks its own sums, sorting, checksum, and multiply results, while the build rejects code that uses registers unavailable on the six-register Nano design.
That common binary turns an architecture argument into a repeatable measurement: 3.49 cycles per instruction for the programmable-logic versions, 6.99 for the custom-chip version, and 57.23 for the bit-serial core under the stated zero-wait-state setup. The next useful extension is to run the same image with realistic memory delays, because the current numbers isolate the cores but don't predict a complete system's speed.