Every production LLM accelerator today picks from a discrete precision menu: INT8, INT4, FP8, FP4. The design space between those modes -- call it fractional precision -- exists algorithmically but has no hardware substrate. FlexPosit ships one, accepted at MICRO 2026. The Posit number format's tapered precision trades fine-grained accuracy near zero for coarser accuracy at the extremes, which happens to match the distribution of quantized LLM weights. The result is group-wise-like accuracy with channel-wise-like hardware regularity: the scaling overhead that makes group-wise quantization expensive on silicon disappears.
The hardware side is a unified bit-serial systolic array with per-column Posit decoders and a global precision controller. Bit-serial means precision is a runtime parameter, not a compile-time constant -- the array runs any fractional precision the controller selects without datapath changes. Compared to BitMoD (group-wise) and OliVe (channel-wise), FlexPosit is 1.8x higher throughput and 1.5x to 2.0x better energy across diverse LLMs at sub-5-bit fractional weights with near-FP16 accuracy. The key claim is that both prior works live on different segments of the accuracy-efficiency curve; FlexPosit defines a new frontier.
The constraint being removed is the forced discrete choice between accuracy and efficiency. Teams designing inference ASICs in 2026 have been choosing between "build for INT4 and lose accuracy" or "build for INT8 and leave efficiency on the table." A fractional-precision substrate that spans both without separate datapaths means the silicon need not be rebuilt each time the accuracy bar moves. Whether Posit displaces BF16 in training pipelines is still open, but for inference silicon where the weight distribution is fixed, this is a structurally better fit.