On-device ML inference on RISC-V has been tractable for two years. Training has not, because the float32 memory budget for gradient storage and optimizer state puts it out of reach on most edge microcontrollers. This paper closes that gap using standard RISC-V extensions that most modern cores already carry: Zfh (scalar float16) and Zvfh (vector float16). The open-source framework built on AIfES delivers complete DNN training at 50% of the float32 memory footprint with minimal model accuracy degradation, plus layer-freezing for transfer learning and fine-tuning scenarios.
The silicon overhead is measured and small: adding Zfh to a RV64GC superscalar out-of-order FPGA softcore costs 1.15% additional LUT6 and 0.05% additional FF at 175MHz. That is the kind of area delta that gets approved in an afternoon. The implication is that any RISC-V core targeting embedded AI that does not already include Zfh/Zvfh is leaving on-device training on the table for approximately 1% die area.
The constraint being removed is the round-trip to the cloud for model updates. In industrial and robotics deployments, cloud connectivity is not always available, and when it is, the update latency means the model is adapting to stale conditions. On-device training with layer-freezing means field adaptation can happen at the edge, in real time, without network access. The team shipping this is betting that AIfES's modular architecture lets operators plug in hardware-specific kernels; the Zvfh implementation they discuss is the template. Any embedded AI team using RISC-V cores should evaluate whether their target core's ISA already includes Zfh and what the AIfES integration cost is. If it does and it is low, on-device fine-tuning is a feature sprint away, not a silicon redesign.