The BoardlessBench project added a fault injector for Advanced eXtensible Interface (AXI) memory traffic in Verilator simulation. Its example is a field-programmable gate array (FPGA) audio engine with a four-sample first-in, first-out (FIFO) buffer and a 0.5 microsecond consumption deadline, the kind of design that can pass an ideal simulation and then crackle when a real system's memory bus gets busy.
The normal run returns a memory response in one cycle and records zero buffer underruns. With fault injection enabled, a fixed random seed inserts bursts of 8 to 32 stalled cycles at a 20 percent rate. The buffer empties, the test detects the underruns, and the same command can reproduce the failure. The generator finds AXI read and write channels in the simulated design, while command-line controls set the stall range and seed.
This doesn't replace testing on the target board, where cache, operating-system, and competing-device behavior create their own timing patterns. It gives the board test a sharper job: measure a real stall distribution, feed that range back into simulation, and require the design to survive it before the next hardware run.