Leo Itoh and Junichiro Kadomoto put CPU designs made by a large language model (LLM) agent onto a field-programmable gate array (FPGA), a chip that can be reprogrammed after manufacturing, and used measurements from the board to choose the next design. One candidate looked faster in a short diagnostic run but slowed down over a longer workload. The board caught the regression, and the team returned to a detailed simulation to find and fix its cause.
The useful number is 9.6x. For 8,000 iterations of CoreMark, a standard embedded CPU benchmark, compiling the design for the FPGA and running it took one tenth the time of a single-threaded register-transfer level (RTL) simulation, which models the chip's logic cycle by cycle. That changes the order of work. A team can use the board to rank many candidates, then spend slow simulation time explaining only the failures and winners.
The paper reports one supervised project, so it doesn't establish that an agent can design a production CPU. It does show a credible evaluation pattern: let cheap hardware measurements narrow the search, while simulation remains the tool for diagnosis. Teams experimenting with AI-generated chip logic should add a long board workload before trusting any score from a short test.