Fraunhofer IPMS demonstrated the first milestone of quasi-monolithic integration (QMI): chiplets placed into structured pockets etched into a silicon wafer, surface-leveled, and wired with back-end-of-line processes that connect to what will become front-end-level interconnect densities. The constraint the approach targets is fundamental. Every existing advanced packaging method (CoWoS, SoIC, FC-BGA, embedded bridge) wires chiplets in the back-end process, which caps connection density at roughly 1-10 connections per square micron. FEOL wiring achieves 100x to 1000x that density. QMI brings chiplets into the same substrate that FEOL interconnects run over, narrowing that gap.
The APECS pilot line is an EU-funded effort, and this is a research milestone, not a production process. The dummy chiplets used in this demonstration are placeholders. What the team validated is the pocket etch, insertion, and planarization process chain - the prerequisites for running FEOL wiring over a heterogeneous wafer with embedded chiplets. The applications named are control electronics, sensors, and MEMS. Those are the domains where chiplet adoption has not happened yet because the die-to-die interconnect overhead is too high for small, power-constrained devices. A MEMS die with chiplet-scale packaging overhead does not fit in a hearing aid or an industrial sensor node.
If the QMI process chain reaches manufacturing maturity in the next 3-5 years, the break-even point for chiplet adoption shifts dramatically toward smaller and lower-power applications. The constraint that keeps monolithic integration dominant in embedded and edge applications is not yield or cost alone - it is the interconnect density floor of current packaging approaches. QMI is the first credible attempt to remove that floor at the wafer level.