Fusible can now generate a Zephyr devicetree overlay, the file that tells the operating system how a board's chips and pins are connected, from the board netlist. It emits bus controllers, attached devices, analog inputs, buttons, and light-emitting diodes for several microcontroller families. When the design doesn't contain enough information, Fusible leaves the device disabled and names the missing fact instead of guessing.
For an Inter-Integrated Circuit (I2C) device, the generator can derive an address from pins tied high or low on the schematic. For a Serial Peripheral Interface (SPI) device, it carries over the chip-select connection and requires a maximum clock rate. It also maps analog-to-digital converter inputs, voltage dividers, and general-purpose input/output pins using Zephyr's own names. The board file remains the source for physical wiring, while a small firmware section supplies facts such as a driver name that no netlist can know.
The release labels the output experimental because it doesn't yet compile the generated overlay against Zephyr. That missing build check should be the next gate. Once it lands, a pin swap in the schematic can update firmware configuration and fail in continuous integration before a firmware engineer discovers the mismatch during board bring-up.