Joel Anthony found a failure that appeared about once every 110,000 control steps between a microcontroller and a field-programmable gate array (FPGA), a chip that can be reprogrammed after manufacturing. Two direct memory access (DMA) channels, which move data without making the CPU copy each byte, had equal interrupt priority. The transmit interrupt could lose the race, leaving the serial peripheral interface (SPI) driver stuck and the control task unable to start its next transfer.
The fix gives transmit the higher priority, aborts a failed transfer cleanly, and adds host tests for busy, error, and failed-start paths. The monitor also checks that every 1 kilohertz tick produces exactly one control step. Anthony then ran the link for 30 minutes at 10.6 megahertz: 1,798,945 steps, 3.6 million frames, zero skipped steps, and zero cyclic redundancy check (CRC) errors. Average latency was 74.4 microseconds.
The code change, failure injection, timing monitor, and hardware soak test answer different questions, and the measured run ties them together. A team with a real-time link should record skipped deadlines and end-to-end latency in the test itself; a bench log that only says "passed" would have hidden the original race.