At Hot Chips 2026, the HBM conversation stopped being about roadmap and started being about physics. Thinner DRAM dies mean worse TSV density headroom and degraded thermal paths. SK Hynix and Samsung have limited capacity at the geometries HBM4 requires. The memory wall that AI hardware architects have been managing as a bandwidth problem is now also a manufacturing capacity problem, and those two constraints compound.
The mechanism is straightforward but easy to dismiss as a packaging concern until it becomes a program schedule concern. Each additional HBM layer requires thinner individual dies. Thinner dies make TSV drilling harder, increase yield sensitivity to stress during stacking, and reduce the thermal conductivity of the stack as a whole. The thermal issue matters because training workloads run HBM continuously at high utilization, and the thermal path from die to package is already the limiting factor on sustained bandwidth. Adding layers does not improve this. The limited manufacturing capacity at these geometries means that demand from one AI hardware program competes directly with demand from every other AI hardware program on the same fab schedule.
For chiplet teams planning HBM4 integration over the next 12-18 months, the practical implication is that the HBM supply curve will not track AI compute demand linearly. GPU vendors and ASIC teams that built their memory bandwidth assumptions on the published HBM4 roadmap need to run a supply-constrained scenario. The loser in this dynamic is any architecture that assumed HBM bandwidth would be elastic. The winner is any architecture that reduced HBM dependency before the constraint hit.