Huawei disclosed its tau scaling law at IEEE ISCAS 2026, and the claim is specific: 381 chips designed over six years without EUV, with the Kirin 2026 achieving 238 million transistors per square millimeter (53.5% denser than Kirin 9030 Pro), reaching the neighborhood of Intel 18A and first-generation TSMC 3nm. The mechanism is not a better process node. It is a 3D layout strategy called LogicFolding that distributes standard cells across vertically bonded wafers using hybrid bonding pitches under 2 micrometers, shortening the critical path RC delay without shrinking the transistor.
The companion signal, published the same week by Peking University's School of Integrated Circuits, is the EDA implication. Every existing 3D flow is pseudo-3D: modules get assigned to dies after synthesis and implemented die-by-die with conventional 2D tools. LogicFolding requires what the PKU team calls true-3D: the placement unit is a standard cell in 3D space, not a module locked to a die. The PKU prototype covers floorplanning and placement with GPU-accelerated optimization across designs up to 24.7 million instances. On open-source industrial benchmarks it delivers 30% total wire-length reduction, 6% WNS improvement, 12% TNS improvement, and 3% peak-temperature reduction with joint thermal optimization.
The long-run read is not about Huawei specifically. It is about what the tau law reveals as a transferable principle: once hybrid bonding pitch clears 3x the top-metal pitch (roughly 2 micrometers at current nodes), cross-layer connections become equivalent to an additional metal layer. That changes what EDA tools need to optimize. True-3D placement is not a research curiosity. The PKU team has a working prototype running at industrial scale. Synopsys and Cadence have been selling 3D-IC flows for chiplet stacking at module granularity. Neither has shipped a true-3D flow that treats the standard cell as the 3D layout primitive. That gap is now visible, named, and has a reference implementation. Expect the major EDA vendors to respond within 18 months or cede the 3D-native design space to open-source challengers.