2D-material transistors are no longer a lab result without a production path. ASML, TSMC, and imec ran MoS2 nFETs and WS2/WSe2 pFETs at 50nm contacted-polysilicon pitch on 300mm wafers with 94% operational yield, using single-patterning EUV. Single-patterning is the critical detail: these devices were fabricated with the same class of scanners running in production fabs today, not research tooling with no manufacturing equivalent.
The integration challenge for 2D materials has always been more process than physics. MoS2 and WSe2 have demonstrated better electrostatic control than silicon at thin geometries for years. What had not been demonstrated was wafer-scale deposition uniformity, contact resistance at production-grade dimensions, and lithography compatibility in a single integrated flow. The 94% yield result, achieved under single-patterning EUV, means that integration gap has closed at the bench-to-wafer scale. TSMC's co-authorship signals this is not imec research in isolation: it is process co-development at the integration level that matters for a foundry roadmap.
EDA teams building PDK support for sub-1nm node candidates should treat this as a 3-to-5 year forward signal. A 2D-material foundry PDK requires new device models, new design rules, and new signoff flows. That work takes 2-3 years after process maturity is established. Imec's 94% yield is early evidence of that maturity. The vendors still assuming silicon-channel CMOS is sufficient through the sub-1nm era now have less runway to maintain that assumption than they did last week.